Tuesday, June 28, 2011

Freescale Technology Forum (FTF) 2011

I had the pleasure to attend this year's FTF Americas in San Antonio, Texas. I've previously attended FTF in Orlando, Florida some years ago, which I enjoyed very much, and San Antonio was a convenient location to visit with family and friends we don't see often, so the trip became a family vacation as well.

I attended the 4-day High-Speed PCB Design track, 4 hours each day. This took most of the session schedule, but I managed to fit in some morning sessions about the new AMP QoriIQ processors, display and audio peripherals, DDR connections, and a couple other things, but I wasn't able to get into the Porting Uboot session I would have liked.

The PCB sessions at first sounded abstract and made my head hurt. Signals don't travel through the copper traces on the PCB, you see. They travel in the spaces between the copper, ie. inside the dielectric core and prepreg, soldermask, outside air, etc instead. (oww...) But days 3 and 4 put that into a less theoretical and more practical sense, and I started to understand things better.
I feel a lot more confident now thinking about fast PCB stuff like PCI-Express, USB3, SATA, etc. which had previously bogged me down in ideas that I knew a tiny bit about, but only enough to be almost afraid of them. Dan Beeker at Freescale and his mentors Ralph Morrison, Rick Hartley, and Dr. Todd Hubing were all great speakers, and interesting to listen to about all this. Ralph is a physics man, Rick is an RF guy, and all four of them treat their designs as physics problems using field theory (electrical and magnetic fields ala Maxwell) instead of traditional circuit theory which breaks at high speeds.

I'd really encourage anyone able to to sit through some seminars from these guys. And they really recommend going to PCB West/East shows.

Rick Hartley offered a list of tech papers and books, which I've duplicated as a Universal Amazon wishlist. You don't have to buy from them, I just like the convenience of making shopping lists this way.

As we made it a family vacation, I didn't check out the vendors room after the courses, and I didn't have free time during the day between courses. Hi Genesi and anyone else I've met before, sorry I missed you.

And a big hello to whoever the guy was that was wearing the Amiga T-shirt on Monday. I didn't get a chance to chat then as I was rushing back into an in-progress course.

Some highlights from the PCB talks:

  • At high speeds, signal energy travels between the copper traces, NOT inside the copper. This is why good coupling to planes is important for return paths.
  • High Speed PCB design is NOT a traditional Circuit Theory problem. instead, it is a physics Field Theory problem (ala Maxwell electrical and magnetic fields)
  • Coupled power/ground planes are very important, both as return paths for fast signals as well as for energy storage to be used by the chips. Fill signal layers with power or ground areas, alternating layers, to maximize power/ground coupling.
  • Put connectors all on same side of PCB to avoid wiring harnesses and other attachments from becoming antennas for parasitic voltages/currents across the board that fail EMI.
  • Take what is said in app notes with a grain of salt. Enough of them are wrong to have resulted in the advice to ignore them unless they are proven correct.
  • Length matching specs are less important than timing specs. A good timing analysis can show that the true need for serpentine length matching can be reduced, saving some noise due to reflections and radiations at serpentine bends, and also save some routing resources on a packed board.
  • Use routed triplets or quints if you have to where a good reference plane is not available. A triplet is one ground trace with two signal traces on either side, sharing the ground trace for a return path. A quint is one ground trace with four signals, two on each side, all sharing the ground trace as a return path. Obviously the quint is not as good as the triplet.
  • If you must gap a plane (try really hard not to), avoid routing signals across the gap, or at least add a reference/return jumper across the gap next to the worrisome signal trace.
  • Energy for a signal switch is pulled from the coupled power/ground plane region near the pin/ball first, then from decoupling cap nearby, then from larger caps further away. Use the highest value cap in the smallest package you can afford. It's better to use single value for all decoupling caps, even if app notes say to use a variety of values. Avoid ferrites, even if app note says to use them, as they can actually hinder energy supply needed in the chip.
  • All grounds are the same ground. Analog, digital, shield, whatever. Many different grounds on a chip symbol are likely connected on the die. Segment things to keep return paths clean, avoiding fast digital returns from mangling slow audio /analog returns by careful component placement or different ground planes (do NOT gap a single plane into islands though!!), or even route a ground on a non-plane layer to keep a slow and potentially wide return path confined. This separate ground thing had me confused for a long time, as I was never able to find anything telling me what the real relationship was between "different" grounds and how to treat them in a PCB layout.
  • A two layer board should be treated as two unrelated single layer board layouts. The layers are too far apart to do any useful plane coupling between them. Route any fast signals with an adjacent routed return path.
  • A four layer board is probably two unrelated two-layer boards. The top two layers should couple to each other well, and the bottom two layers should couple to each other, but the top and bottom do not couple together well through the center core as they are still rather far apart there.
  • I'll add a few more as I remember them, I forgot one already before I got to typing it here.

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